The implemented circuit requires only one dc power supply to feed the whole gate driver for the three-phase system.The proposed circuit is based on commercially available MOS-gate driver ICs (MGDs) for large-scale applications, which may reduce the total cost of implementation of NPC inverters.
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Ir2110 Bootstrap Capacitor Calculation Thesis Driver For TheThese results also suggest that for achieving safe operation of snubberless power switches during transients, a hybrid implementation of each NPC phase leg, consisting of MOSFETs with voltage ratings at half the DC bus voltage and of insulated gate bipolar transistors rated at the total DC bus voltage, is recommended. Switch Q3 voltage waveform (20 Vdiv, 20 sdiv). Conventional recharging process of the bootstrap capacitor C3. Figures - uploaded by Walter Suemitsu Author content All figure content in this area was uploaded by Walter Suemitsu Content may be subject to copyright. Ir2110 Bootstrap Capacitor Calculation Thesis For Free Public FullDiscover the worlds research 20 million members 135 million publications 700k research projects Join for free Public Full-text 1 Content uploaded by Walter Suemitsu Author content All content in this area was uploaded by Walter Suemitsu on Sep 07, 2014 Content may be subject to copyright. Only one dc power supply is required to feed all the gate drivers for the thr ee-phase system. Detailed design procedures are presented, which include the pr o- tection circuits for avoiding hazardous switching states of the power switches. These results also suggest that for achieving safe operation of snubberless power switches during transients, a hybrid implementation of each NPC phase leg, consisting of MOSFETs with voltage ratings at half the dc bus voltage and of insulated gate bipolar transistors rated at the total dc bus voltage, is recommended. Index T erms Charge pump technique, gate drive circuit, switch-voltage balancing, three-level neutral-point-clamped (NPC) inverter. I. I NTRODUCTION M UL TILEVEL inverters ha ve been considered a high- potential technology for high-power high-voltage ap- plications, since they can offer some advantages o ver their two-level pulse width modulated counterparts, such as reduced switch-voltage ratings, reduced switch dvdt stresses, and out- put voltage waveforms with impro ved spectra at lower switch- ing frequencies 13. In particular, neutral-point-clamped (NPC) inverters ha ve been receiving increased attention re- cently for the integration of renewable energy sources to the Manuscript received June 16, 2008; revised September 15, 2008. First published October 31, 2008; current version published April 1, 2009. Thus far, special concerns on the controls of these inverters hav e been extensively reported 914. Nevertheless, low-v oltage applications of three-level NPC inverters are still very restricted, and fe w works on this topic have been done 7, 8, 15. Although the use of integrated gate drive circuits MOS-gate driv er ICs (MGDs) for control- ling two-level in verters are very common, this has not yet been the case for multilevel in verters. The development of lo w-cost and reliable gate drive circuits may considerably reduce the total cost of implementation of multilevel in verters, and then make them a competitive solution in industries. In 7 and 16, gate drive circuit was proposed based on the bootstrap charge pump scheme, which was applied to a three-level NPC three- phase inverter and to one phase leg of an eight-le vel oating source multilevel in verter, respectiv ely. In those w orks, power MOSFETs were used, and the gate drivers were composed of discrete components. This paper is focused on the implementation of the charge pump technique with commercially available MGDs, generally applied to two-level in verters, for the power switches of three-level NPC in verters. ![]()
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